1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device to be employed as a microprocessor cache memory that can quickly align data after the data is read.
2. Description of the Prior Art
A microprocessor frequently incorporates a cache memory. To read data from the cache memory and execute an arithmetic operation with the data, the data shall be aligned. For this purpose, an aligner is disposed between the cache memory and an arithmetic circuit.
According to prior art, data read out of the cache memory is provided to the aligner through a sense amplifier. Thereafter, the aligner, which comprises a group of CMOS logic gate transistors or transfer gate transistors, aligns the data and transfers the same to the arithmetic circuit.
FIG. 1 shows a conventional arrangement from a memory array 1 to an aligner 10. This arrangement processes a signal of 4 bytes, i.e., 32 bits. Data in the memory array 1 is selected by a column selector 2 and read out. The read data is amplified by a sense amplifier 3, and aligned by the aligner 10. The aligner 10 includes wires W and selectors 4 to 7. The aligner 10 transfers the data to an arithmetic circuit.
Each of the selectors 4 to 7 may comprise a group of CMOS logic gate transistors for processing respective bits of the data. FIG. 2 shows such a circuit disposed in the selectors to process one bit. The circuit of FIG. 2 comprises AND gates A1 to A4, NOR gates NOR1 and NOR2, and a NAND gate NAND. Each of the selectors 4 to 7 involves eight such circuits to select one of four bytes according to control signals AE to DE and provides an output signal Z from the NAND gate NAND.
The prior art of FIG. 1 reads data from the memory array 1, which serves as, for example, a cache memory. The read data is passed through the column selector 2 and sense amplifier 3, and applied to the aligner 10, which aligns the data. This prior art arrangement has several drawbacks.
Firstly, to transfer a data output of the sense amplifier 3 to the selectors 4 to 7, the wires W must be arranged. The wires W have a very complicated arrangement and occupy a large area, thereby increasing the capacitance and load.
Secondly, the selectors 4 to 7 that may be composed of CMOS logic gate transistors as shown in FIG. 2 or transfer gate transistors (not shown), require a large number of logic gates arranged in several stages. This may increase the delay. This delay and a delay caused by the wires W deteriorate the processing speed in reading data from the memory and transferring the same to the arithmetic circuit.